1. Field of the Invention
This invention relates generally to digital signal processing units and, more particularly, to techniques for test signal transfer between the host processor and the test system, the test system including an emulator unit and a target processor unit.
2. Background of the Invention
As digital signal processor units and the software programs that are executed thereon have become more complex, the testing of both the hardware apparatus and the software programs has become increasingly difficult. The expanding number of components implementing the digital processing units results in a correspondingly expanding number of potential problems. Furthermore, a tendency to fragmentation of the testing procedures among the system has developed. In an attempt to standardize the testing procedures, the JTAG (Joint Test Action Group) protocols have been developed. The JTAG protocols provide standardized test procedures that can be used with a wide variety of processing unit platforms. The protocol consists of standardized commands to which standardized responses are expected. Any departure from the expected response indicates the presence of a error.
The testing procedure can be understood by reference to FIG. 1. A host processor 12, in association with an integrated development environment (IDE), generates a command that will test or provide a debug access to a portion or a function of a target system or a target processor peripheral unit 16. The command generated by the host processor unit 12 is transferred to the emulator unit 14 by communication bus 11. In the emulator unit, the command is reformatted to a command or commands that can be executed by the target processing unit 16. The target processing unit 16 executes the reformatted command and transfers the resultant data to the emulator unit 14. When the emulator unit 14 has all of the resultant data, the emulator unit 14 transfers the resultant data to the host processor unit 12 by the communication bus 11. The host processor unit then analyzes the data to determine whether the execution of the command by the target processor unit 16 was accurate.
Referring to FIG. 2, a more detailed description of the debug and test process for validating a target system or target processor application unit is shown. In step 201, the host processor transmits a command to the emulator unit. The command includes whatever data is necessary for implementation of the command. Included in the command is the instruction that, upon a preselected event, the results of executing the command by the target processing unit command will be transferred to the host processing unit. The emulator unit reformats the command from the host processing unit into a format that is executable by the target processing unit and applies the reformatted instruction to the target processing unit in step 202. In step 203, the target processing unit executes the applied command and transfers the resultant data, i.e., the data resulting from the execution of the command, to the emulator unit. Upon the identification of the event specified in step 201, the resultant data is transferred to the host processor unit in step 204. The event is either the completion of the execution of the command or an event related to the completion of the execution of the command. In step 205, a determination is made by the host processing unit whether the command for which the data has been received in the last command in the test sequence. If the command for which the resultant data has been received is the last data in the sequence of commands to be applied to the target processing unit, the delivery of commands to the target processing unit is ended. When in step 205, the just completed command is not the last command in the sequence to be applied to the target processing unit, then the process proceeds to step 206. In step 206, the next command in the sequence of commands to be applied to the target processing unit becomes the (current) command and the process proceeds to step 201 wherein process is repeated.
While the foregoing process can provide a suitable technique for testing hardware and software components by a host processing unit, one problem that is encountered is the traffic between the emulator unit 14 and the host processor unit 12. As is clear from the foregoing description, the host processor issues one command to the emulator unit 14 requiring activity over the communication bus 11. When the results of the execution of the command executed by the target processing unit 16 are complete, a second access to the communication bus 11 is required to transfer the resultant data from the emulator unit 14 to the host processing unit 12. The host processor then repeats process for the next command. Thus, the testing of the target processing unit 16 requires two communication bus 11 accesses for each command tested. The traffic on the communication bus 11 typically has components in addition to the traffic between the host processing unit 12 and the emulator unit 14. The frequent communication between the host processing unit 12 and the emulator unit 14 can interfere with other traffic over the communication bus 11.
A need has therefore been felt for apparatus and an associated method having the feature that the communication between the host processor and the emulator unit over the communication bus can be improved. It would be a further feature of the apparatus and associated method to reduce the traffic between the host processing unit and the emulator unit during the testing of a target processing unit.